From: ptkwt@...1.aracnet.com (Phil Tomson) Date: 2003-04-04T06:16:26+09:00 Subject: Re: Any Hardware/EDA engineers out there? In article <20030403180744.GC29313@vor-lord.ftc.agilent.com>, Brett H. Williams wrote: >On Apr 4, Phil Tomson wrote: >> In article <20030403170348.GB28569@vor-lord.ftc.agilent.com>, >> Brett H. Williams wrote: >> >On Apr 3, Phil Tomson wrote: >> >> Just curious: are there any other hardware engineers or EDA software >> >> engineers out there in RubyLand? >> >> >> >> I've been thinking about starting some sort of RubyEDA site where we could >> >> post Ruby packages/applications which are related to EDA - like RHDL. >> >> >> >> This would be a way of promoting the use of Ruby in the EDA/hardware >> >> design community. >> >> >> >> Anybody else got packages that would be appropriate to put on a RubyEDA >> >> site? >> > >> >Here we have some C++ libs wrapped into Ruby for manipulating >> >verilog, LEF, DEF, and some other in house EDA formats. It's also used in >> >several other Ruby-only tools for ASIC design. >> >> Can you elaborate on 'for manipulating verilog'? > >Pretty much anything with (mostly) structural verilog netlists. Tools built on >top of this include scan chain stitching, scan chain verification, netlist >quality check, test vector generation netlist preparation, etc. Currently we >don't do anything with RTL, for example, just post-synthesis netlists. > >Lots of quick scripts are also written by individual chip designers who have a >need to automate any kind of hooking things up, disconnecting things, etc. >Especially at the beginning of a chip design cycle (where netlist quality is >poor and needs to be propped up for early builds) and at the end (where full >automation breaks down and things are tweaked to take care of small changes and >remaining errors of various kinds), it gets pretty heavy use. > >It's also used to convert between the above listed formats. > >Something similar to this probably exists in all kinds of chip design shops all >over the country. It'd be nice if there was a robust, full-featured open >source version of such a thing. > So you essentially have a Verilog parser written in Ruby? Is this something that you could release? Phil