From: ptkwt@...1.aracnet.com (Phil Tomson) Date: 2003-03-21T18:21:32+09:00 Subject: Re: Strong advantages over Python In article <3E7A88A0.20202@day-reynolds.com>, Lennon Day-Reynolds wrote: > >Finally, the flexibility of the syntax allows for some very interesting >domain-specific language work, like the make replacement and HDL >mentioned recently on this list. Python can easily be extended with >classes and functions for specific domains, but the inflexible syntax, >esp. with its required indentation and parenthesis, basically forces you >to make your DSL look just like Python, or do a full >lexing/parsing/evaluating cycle on a new syntax. With Ruby, much like >with Perl, you have just enough "wiggle room" to create a syntax that >"just works" for some subset of possible uses. > Good point. Ruby's blocks allow you to easily create domain specific languages. I get the idea that it would have been very difficult to do RHDL in Python for two reasons: 1) Ruby's code blocks 2) continuations which allowed for implementing 'wait' statements So in RHDL I can do: class MyCounter < RHDL::Design include RHDL def initialize(clk,rst,counter) super() define_behavior { #this is really a code block that looks like #it's just part of the syntax of the HDL process(clk) { #another code block if clk == '1' && clk.event if rst == '1' counter.assign 0 #I'd like to have a '<-' operator! else counter.assign { counter+1} end } process(counter) { wait { $simTime == 50 } #continuation required puts "counter = #{counter}" } } end end #instantiate and simulate: rst = Signal(Bit('0') clk = ClkGen.generate('0',20,20) #0 for 20 cycles, then 1 for 20 cycles counter = MyCounter.new(rst,clk) include TestBench 100.times { #simulate for 100 cycles, this may change to: step(100) step } So the code blocks in this RHDL example show how I've been able to adapt Ruby to work as an HDL. Those who are familiar with VHDL will notice the resemblence. The define_behavior, process, and wait methods take code blocks so that those methods just end up looking like HDL syntax. Recently a Python-based HDL called MyHDL was released, and while it does have some interesting features, it doesn't really end up looking much like an HDL (such as VHDL or Verilog) - in MyHDL you define functions which are generators (this approach has merits, but it doesn't end up making Python look like an HDL). BTW: I'd like to have an '<-' operator instead of having to use the 'assign' methods in the example above. See my post proposing an overloadable '<-' operator. Phil