From: Clifford Heath <no@...>
Date: 2008-01-30T15:04:56+09:00
Subject: Re: Treetop parser (or PEG in general?) questions

Phil Tomson wrote:
> Just to up the ante a bit:
> In VHDL entity declarations can have port declarations in them as can
> component declarations:
> 
>   entity Foo is
>     port( a,b : in bit;  c : out bit);
>   end Foo;
> 
>   --later
> 
>   component CPU is
>     port( clock : in bit;
>              data_bus : inout bit_vector( 15 downto 0);
>              address_bus : out bit_vector( 31 downto 0)
>           );
>    end CPU;
> 
> There should only be 1 entity declaration in a file, but there could
> be multiple component declarations (or none) in a file.  I'd like to
> extract the entity port declaration and component port declarations
> (keeping a list of component ports).
> 
> Any suggestions?

Same sort of thing: scan any rubbish not looking like "entity", then,
continuing until you see the matching 'end', scan rubbish until you
see 'port'. Scan that, repeat until you see the end of the entity,
then do the same sort of thing for component.

Might be quicker to build most of the grammar if you have multiply-
nested things terminating in 'end', but s.t. like this should work:

rule file
  (!'entity' .)* entity components
end

rule entity
   'entity' ports 'end'
end

rule ports
  ((!'port' .)* port)*
end

rule port
  'port' port_decl
end

rule components
  ((!'component' .)* component)*
end

... etc.


Clifford Heath.