From: tsuraan <tsuraan@...>
Date: 2005-08-03T03:42:11+09:00
Subject: Re: [question] Verilog RTL parser in Ruby?

> That said, I believe you can use Icarus (open source Verilog
> simulator and now synthesis tool) to synthesize to some of the older
> Xilinx architectures.  Also, it can't be impossible to get the needed
> information (Synplicity, for example, makes FPGA synthesis tools that
> target Xilinx, Altera and others' parts), but there may be NDA forms to
> sign.  I suspect the bitstream files are the tricky part.

That's cool to know.  I'll have a look that those projects.

> Actually there are lots of possibilities if you have Verilog/VHDL parsers:
> 
> 1) You could create translators between the two or to cycle-based
> C or SystemC.
> 2) You could create a testbench generation tool.  The tool would look at
> your toplevel entity/module and then it could create the skeleton for your
> testbench.  Of course, you don't need a full parser for this, but if you
> have one it'll make things easier.
> 3) It would be possible to create verification and code analysis tools.
> 4) Synthesis/Tech mapping.  Nothing would stop you from creating
> VHDL/Verilog or EDIF netlists (gate level).  Because Ruby is a very
> flexible language it would be interesting to use it to develop an
> experimental synthesis platform where you could easily try new algorithms,
> datastructures, etc.
> 
> ....lots of possibilities.

Ok, that's cool.  I was sort of hoping you'd point me towards the
elusive OpenXilinxTools, the mythical totally free implementation of
the Xilinx software, but I guess I'll have to keep looking :)