From: ptkwt@... (Phil Tomson) Date: 2004-07-16T13:52:17+09:00 Subject: Re: Do you want ":=" operator? In article , Xiangyu Yang wrote: >>Right. But not all object states or values can be changed that way, >>and there is no meaningful default operation for such a behaviour. >>Thus, it makes more sense to use the appropriate #<< or #assign >>mechanism. > >>-austin >>-- >>Austin Ziegler * halxsxtaxuxx@gxxxxxxlx.cox >>* Alternate: ausxin@hxaloxxtxxxuex.xa > >I can't use << and other operators, for they are all meaningful in my >CPU model and have precedence problem. yes, usually these operators ('<<' and '>>' ) are used for shifting or rotating registers in hardware descriptions. You can always define an 'sl' or 'shift_left' method for your classes I suppose, but '<<' and '>>' are widely understood especially among Verilog programmers. >And I can't force anybody to >program "R0.assign(R0&R1)" for my CPU, otherwise I will be kicked to >death. Yeah, hardware designers are a tough crowd ;-) >I have to translate "Rx=..." to "Rx.assign ...", then eval the >latter. Wow, you're really serious about this ;-) >The ":=" need not be supported by all classes. To use it or not, it's >the programmer's choice. Quite true. Phil